In Figure 10, it can be seen load regulation is better with higher DC gain, and worse with lower DC gain. At high frequencies, a high-frequency compensator pole can help filter out high-frequency noises.
Take a GM-Type compensator below as an example. Since a GM-Type compensator has one zero and two poles, it is quite suitable to compensate peak current-mode buck converters. First pole can be obtained from R gm and C comp , the other pole from R comp and C gm , and a zero from R comp and C comp.
Step 1 : Set the crossover frequency i. Step 2 : Set the zero of the compensator to cancel the pole of the peak current-mode buck topology. Step 5 : From Equation 12 , the DC gain, increased by the compensator at the crossover frequency, can be calculated as Step 7 : Substitute all the above numbers into Equation 13 , then enter the equation into Mathcad, and the Bode plot of the compensator can be drawn, seen in Figure In this section, the SIMPLIS tool is used to simulate the peak current-mode buck converter and to substantiate the closed-loop frequency response analysis.
The closed loop of this current-mode buck converter incorporates a current sensor, a compensator, and a slope compensation circuit. Figure It demonstrates that the simulation result closely aligns with the analytical result, derived by Mathcad, and the bandwidth and phase margin are 34kHz and Figure 16 has exhibited the benefits a compensator can provide.
First, a compensator black dashed line enhances DC gain in the low frequency range. The open loop response red line , combined with the compensator response black dashed line , makes the closed loop response blue line. Second, a compensator increases bandwidth, as in Figure 16, the crossover frequency in blue is greater than that in red. Third, a compensator adds one high-frequency pole, which improves high-frequency noise immunity at high frequency, the blue line drops faster than the red line.
Fourth, the zero of a compensator helps achieve a sufficient phase margin. An actual measurement setup is presented in Figure 17, and an AC perturbation signal is injected into point R. The gain and phase plot can be obtained by measuring the output point A versus the input point R.
From the right-hand plot of Figure 17, the measured result green line shows good agreement with the analytical result red line. Depending on these, I have designed my compensator and I can't for the life of me figure out if what I've done is right. Here is the schematic of output filter model:.
To find out the required gain shift and phase boost, I have set the gain of VCVS error amplifier as 1. The height of sawtooth signal is 2V and the maximum supply is 3. The small signal gain of modulator would be 1. The resistor divider contributes to an attenuation of 1. The open loop magnitude response consisting of Filter, PWM modulator and resistor divider hence starts with at mdB.
I've marked the required gain and phase boost that compensator has to provide at kHz. So I have designed the type-3 error amplifier with above points in mind:.
The shape of curves looks fine but the stability margins don't seem right. A gain margin of dB? Is there anything wrong in my results? This simulation uses VCVS with a high gain of k. When I use an amplifier with a gain of , the response of compensation network is not like the one shown above. Because of the pole at the origin, the gain should start rolling-off from very low frequencies which happens when gain is k.
But with a gain of , the pole appears at a frequency near to Hz. I understand that I don't have a very clear idea of what is actually expected. But I want to know if the little that I've understood and worked on is correct or not. Any help is appreciated. Your approach looks sound from a theoretical perspective. From a practical perspective, the exact phase margin point isn't a concern so long as you have dB or less gain.
Your gain line looks fine to me. Your simulated results are going to be somewhat different from reality even if your components match the values you chose, as parasitics and other delays not considered by your model will affect the overall loop response.
That being said, this sort of theoretical computation is generally the first step in designing a stable compensation network. This article will discuss both low voltage low power converter and low voltage high power converter. The efficiency of the converter can be improved using synchronous version and resonant derivatives. The other method of improving efficiency is to use Multiphase version of buck converters. The improvement of efficiency with multiphase inverter is discussed at the end of the article.
The basic buck converter consists of a controlled switch, a diode, capacitor and controlled driving circuitry. The time for which the switch is ON during the whole period is known as Duty cycle. The value of duty cycle D ranges between 0 and 1. The basic circuit diagram of buck converter can be seen below. The average output voltage of Buck converter is controlled using two different ways i.
But PWM is preferred most of the time for operation of buck converter. A buck converter operates in two types of conduction modes i.
The inductor current I L never become zero through the switching period. In contrast, the inductor current in DCM D iscontinues C onduction M ode become zero for some time in switching period. Waveforms for both continuous and continuous conduction modes are shown in the figure below.
All the discussion in this article is for CCM buck converter which is required for most of applications. As we have discussed in the previous topic that there are two modes of operation in buck converter i.
The converter is said to be operating continuous conduction mode if the load current never become zero during the complete cycle. If the inductance value is reduced, then the ripple will increase.
Further reducing the inductance value will increase the ripples such that ripples will become more than load current. At that time, the operation of converter will change from CCM to DCM because the load current will become zero for some instant.
Increasing the load resistance will reduce the load current. The above graph will become as shown below. The current become zero just for zero interval of time and then start increasing.
Further increasing the load resistance will reduce the load current further which will change the operation of buck converter from CCM to DCM.
The operation mode immediately changes when load current reduces more than ripples. The following graph shows the DCM mode.
The load current now prematurely drops to zero. By prematurely means that the current goes to zero before the switch is turned on. Properties of CCM. Some of the properties of CCM are given as. More technically speaking, the DCM occurs due to switching ripples in inductor current.
Or it occurs due to reversing the capacitor voltage polarity such that it violates the assumptions made for realizing the switch.
In simple words, the inductor current ripples are more than the load current. So, during off time, the load current starts decreasing till it become zero. Mostly in PWM buck converter it happens when both voltage and current of the circuit become zero for a short interval of time.
During this interval, a new shape of the circuit forms which is normally not possible. This is known as DCM mode which is sometimes intentionally designed intentionally designed. The overall D Ts remain unchanged during DCM because the conduction of the signal is controlled by the control signal D. And this is independent of circuit operation however, D Ts is divided into two new portions i.
D 2 and D 3 as shown in the above figure. D2 and D3 are additional unknown parameters which make the calculation a little bit complex. Properties of DCM. Some of the properties of the converter changes when converter starts operating in DCM. Some of those properties are given below. The working operation of buck converter can be explained in two modes. Both modes are explicitly discussed here. By turning ON the switch, the diode will become reverse bias to the applied input. Therefore, all the input current will flow through inductor.
Hence the DC input current I dc flowing in the circuit is equal to the inductor current. The inductor will charge during turn ON time. This current further divide into load current Io and capacitor current Ic.
The inductor voltage V Lon during this period is the voltage difference between applied DC voltage V dc and output voltage V o. The average voltage across inductor V L is zero according to volt second balance.
Recalling the duty cycle equation, the turn ON time t on is the product of duty cycle D and total time T. By putting the value of V L we get. The final result shows the current slop of inductor current during on time. The wave form shown given below shows the rippling current that first increase in ON time and then reduces with negative slop.
After turning OFF the switch, the mode 1 changes to mode 2. In this mode the polarity of inductor reverses and it start acting as a source. The current in this mode flows due to the stored energy in the inductor.
The DC source is disconnected during this period. Therefore, the current flows in the circuit till the inductor discharges. The voltage appearing across the inductor is equal to the load voltage with negative polarity. After turning OFF the switch, the polarity of inductor changes which make the diode forward bias.
The anode voltage become more positive than cathode during this period and hence starts conducting. The turn off time t off can be derived from turn on time t on in duty cycle. The turn off time can be written in the final form as. The slop of inductor current can be found once again by voltage current equation of inductor. Therefore, both minimum peak and maximum peak of the current need be found. By putting the values that we have been discussed in previous two modes of operation, the form of equation will become as given.
Further simplifying the above equation, the final form of the minimum inductor current can be achieved as given below. By putting the previously discussed values in the above equation, we will get. Further simplifying the above equation, we will get the final form as given below for maximum inductor current. The buck converter needs to be considered in steady state for finding transfer function.
This consideration will make the calculations easy for finding transfer function. The average voltage across the inductor is zero in steady state according to volt second balance.
Further, the inductor will act as a short circuit in steady state to a pure DC. By putting the values of V Lon , t on , V Loff , t off in above equation, the result will become. Further simplifying will result. The final form of the transfer function is. Therefore it shows that the average output voltage is always less than the applied input voltage. This section will discuss the designing of components used in buck converter with their ratings. This section will describe the important aspect of inductor required for buck converter.
This includes two main ideas i. Critical inductance Lc is the minimum value of inductance at which inductor current reaches zero. Therefore, it is most important condition for operating buck converter in discontinues mode. In other words, the value of inductor is chosen below than critical inductance for operating buck converter in discontinuous mode.
The requirement is set by means of minimum percentage load. For operating buck converter in CCM mode, the inductor value is chosen more than critical inductance. The value of critical inductance can be found directly by simplifying the equation. We get the following result after solving the above equation. This is the most important equation for finding critical inductance which will decide the operation mode of buck converter.
Where these quantities are selected as given. The peak current rating of inductor can be found using maximum value of the inductive current I Lmax. The maximum inductor current occurs at maximum load.
The peak current rating of inductor can be found using the equation of maximum inductor current as given as. The simplified form is given below which will define the rating the rating of inductor current. This section will discuss both current and voltage rating of a switch for buck converter. For ideal diode, the V switch-max is equal to V dcmax while for non-ideal diode; V switch-max is equal to V dcmax plus V F.
The current rating for a switch is calculated based on average current. By drawing the switch current waveform, the average value of the current can be calculated. The average current for the switch is calculated here. Overall inductor current is equal to switch current and diode current using KCL.
During the turn ON time, the inductor current is equal to switch current while the inductor current is equal to diode current during turn OFF time. By putting the values in above equation, the result will become as given below. Further simplifying and putting the previously discussed value.
The final form of the equation of current rating for the switch become. Shotkey diodes are preferred for the discharging of buck converters due to fast recovery action. These diodes are known as fast recovery diodes so preferable for high frequency operation i.
This section will discuss the current and voltage rating of shotkey diode for buck converter. It is given in the data sheet of the component. Where, the value of V sw is calculated at maximum load current.
The same approach is adopted for calculating current rating for diode as it was adopted for the calculation of switch. The average forward diode current is calculated from the current waveform of the diode. As diode conduct during off time of the switch therefore, t off is considered in the calculation.
By putting values in the above equation, the result will become. Simplifying the above equation will result. By putting previously discussed values and simplifying, the result will become.
This will lead to one of most important result that is given below. The following wave form is the diode current wave form. It provides ease in finding average value. This section will discuss the important parameter for a capacitor under which the capacitor can be operated in safe mode. Furthermore, the capacitor is designed such that the required functioned is performed.
The capacitor is designed and chosen such that the maximum capacitor voltage must withstand the maximum output voltage. Ideally the maximum capacitor voltage V cmax is. As given as. The case is a bit different for particle capacitors. This contribution made by ESR can be suppressed by using following methods. The designed capacitor will provide a path for AC ripples of inductor current while pure DC current will flow into the load.
That is how the capacitor will act as a filter. The waveform of the capacitor current will look as shown below. It can be seen form the below given waveform capacitor current w. By putting the values and simplifying the result will become. The final result for minimum capacitance will be as shown below. The capacitor is designed such that the maximum input voltage will be with stand by capacitor voltage.
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