Pipeline hazards pdf

Control dependences determine the ordering of an instruction with respect to a branch instruction so that an instruction i is executed in correct program order. There are two general constraints imposed by control dependences:. Having introduced the various types of data dependences and control dependence, let us discuss how these dependences cause problems in the pipeline.

Dependences are properties of programs and whether the dependences turn out to be hazards and cause stalls in the pipeline are properties of the pipeline organization. Data hazards may be classified as one of three types, depending on the order of read and write accesses in the instructions:. Add modifies R1 and then Sub should read it.

If this order is changed, there is a RAW hazard. Instruction i has to modify register r1 first, and then j has to modify it. Otherwise, there is a WAW hazard.

There is a problem because of R1. If some other register had been used, there will not be a problem. Instruction i has to read register r1 first, and then j has to modify it.

Otherwise, there is a WAR hazard. The hardware can do the renaming or the compiler can do the renaming. The use of the result of the ADD instruction in the next three instructions causes a hazard, since the register is not written until after those instructions read it.

The write back for the ADD instruction happens only in the fifth clock cycle, whereas the next three instructions read the register values before that, and hence will read the wrong data. This gives rise to RAW hazards. The first instruction is a branch and it gets resolved only in the fourth clock cycle.

So, the next three instructions fetched may be correct, or wrong, depending on the outcome of the branch. This is an example of a control hazard. Now, having discussed the various dependences and the hazards that they might lead to, we shall see what are the hazards that can happen in our simple MIPS pipeline. Let us look at the speedup equation with stalls and look at an example problem.

To summarize, we have discussed the various hazards that might occur in a pipeline. Structural hazards happen because there are not enough duplication of resources and they have to be handled at design time itself. Data hazards happen because of true data dependences and name dependences.

Control hazards are caused by branches. The solutions for all these hazards will be discussed in the subsequent modules. Skip to content Increase Font Size. In simple pipelining processor, at a given time, there is only one operation in each phase. The initial phase is the IF phase. So, at the first clock cycle, one operation is fetched. When the next clock pulse arrives, the first operation goes into the ID phase leaving the IF phase empty.

Now, this empty phase is allocated to the next operation. So, during the second clock pulse first operation is in the ID phase and the second operation is in the IF phase. For the third cycle, the first operation will be in AG phase, the second operation will be in the ID phase and the third operation will be in the IF phase. In this way, instructions are executed concurrently and after six cycles the processor will output a completely executed instruction per clock cycle.

Has this instruction executed sequentially, initially the first instruction has to go through all the phases then the next instruction would be fetched? So, for execution of each instruction, the processor would require six clock cycles. But in a pipelined processor as the execution of instructions takes place concurrently, only the initial instruction requires six cycles and all the remaining instructions are executed as one per each cycle thereby reducing the time of execution and increasing the speed of the processor.

Parallelism can be achieved with Hardware, Compiler, and software techniques. To exploit the concept of pipelining in computer architecture many processor units are interconnected and are functioned concurrently. In pipelined processor architecture, there are separated processing units provided for integers and floating point instructions.

Whereas in sequential architecture, a single functional unit is provided. In static pipelining, the processor should pass the instruction through all phases of pipeline regardless of the requirement of instruction.

In a dynamic pipeline processor, an instruction can bypass the phases depending on its requirement but has to move in sequential order. In a complex dynamic pipeline processor, the instruction can bypass the phases as well as choose the phases out of order. In 3-stage pipelining the stages are: Fetch, Decode, and Execute. This pipelining has 3 cycles latency, as an individual instruction takes 3 clock cycles to complete. For proper implementation of pipelining Hardware architecture should also be upgraded.

The hardware for 3 stage pipelining includes a register bank, ALU, Barrel shifter, Address generator, an incrementer, Instruction decoder, and data registers. In a typical computer program besides simple instructions, there are branch instructions, interrupt operations, read and write instructions.

Pipelining is not suitable for all kinds of instructions. When some instructions are executed in pipelining they can stall the pipeline or flush it totally. This type of problems caused during pipelining is called Pipelining Hazards. In most of the computer programs, the result from one instruction is used as an operand by the other instruction.

When such instructions are executed in pipelining, break down occurs as the result of the first instruction is not available when instruction two starts collecting operands. So, instruction two must stall till instruction one is executed and the result is generated. This type of hazard is called Read —after-write pipelining hazard.